An FPGA packet communication protocol
Автор: Adamovich Igor Alekseevich, Klimov Yuri Andreevich
Журнал: Программные системы: теория и приложения @programmnye-sistemy
Рубрика: Программное и аппаратное обеспечение для супер ЭВМ
Статья в выпуске: 1 (44) т.11, 2020 года.
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When creating computer boards with FPGA or application-specific chips, it is often needed to connect several chips. Existing available buses do not have all the properties required by the authors' task at hand: packet transmission, using a small number of GPIO pins, sufficient bandwidth.We describe a packet communication protocol that uses GPIO pins and has bandwidth up to 10 MB/s at a frequency of 20 MHz.
Half-duplex communication, credit-based flow control, data serialization/deserialization, finite state machine, shift register, hardware description language
Короткий адрес: https://sciup.org/143170860
IDR: 143170860 | DOI: 10.25209/2079-3316-2020-11-1-57-78
Список литературы An FPGA packet communication protocol
- R. Tsugami, Y. Shibata. “FPGA implementation of lightweight communication protocol processing for IoT”, CISIS-2018, Advances in Intelligent Systems and Computing, vol. 772, eds. L. Barolli, N. Javaid, M. Ikeda, M. Takizawa, Springer, Cham, 2019, pp. 506-517. DOI: 10.1007/978-3-319-93659-8_45
- R. S. Correa, J. P. David. “Ultra-low latency communication channels for FPGA-based HPC cluster”, Integration, 63 (2018), pp. 41-55. DOI: 10.1016/j.vlsi.2018.05.005
- R. S. S. Kumari, C. Gayathri. “Interfacing of MEMS motion sensor with FPGA using I2C protocol”, 2017 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS) (17-18 March 2017, Coimbatore, India), pp. 1-5. DOI: 10.1109/ICIIECS.2017.8275932
- G. Yoon, J. Kim, G.-Y. Kim, B. Son, H. Yoo. “Multiple RS-485 interface management FPGA design for Power micro-metering”, 2019 10th International Conference on Power Electronics and ECCE Asia (ICPE 2019 - ECCE Asia) (27-30 May 2019, Busan, Korea (South)), pp. 2635-2640.
- N. N. Bespalov, Y. V. Goryachkin, D. V. Tundykov. “Software implementation control devices on FPGA for data interchange on SPI interface”, Scientific and Technical Volga region Bulletin, 2016, pp. 75-78 (in Russian).
- V. S. Starshinov, S. A. Tkachev. “Development of IP-Core for connecting AXI and SPI interfaces using microprocessor systems in conjunction with FPGAs”, Proceedings of research papers in 10 parts. 1, ed. D. N. Dostovalov, Novosibirsk State Technical University, Novosibirsk, 2018, pp. 110-117 (in Russian).
- R. Nawrath, R. Czerwinski. “FPGA-based implementation of APB/SPI bridge”, International Conference of Computational Methods in Sciences and Engineering 2018 (ICCMSE 2018), AIP Conference Proceedings, vol. 2040, AIP Publishing, 2018, 4 pp. DOI: 10.1063/1.5079145
- A. V. Rutkevich, A. A. Veykov, I. Y. Sysoev. “IP-Core SD device development”, Problems of Advanced Micro- and Nanoelectronic Systems Development (MES), 2016, no.3, pp. 186-190 (in Russian).
- M. I. Chemodanov. “Interface organization for realization AXI-Lite protocol over Xilinx FPGA”, Proceedings of the 1Russian National Scientific Conference. 2, Kachalin Alexander Vasilievich, 2017, pp. 261-268 (in Russian).
