Memory controller and its interface using AMBA 2.0
Автор: Hitanshu Saluja, Naresh Grover
Журнал: International Journal of Engineering and Manufacturing @ijem
Статья в выпуске: 4 vol.9, 2019 года.
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This paper elaborates the AMBA bus interface bridge between memory controller and other supporting peripheral. The work claims the integration with FIFO, RAM and ROM with slave interface and the master of AHB bus. The AHB master initiates the operation and generates the necessary control signal. Memory controller is implemented with finite state machine considering with all the peripheral works in synchronous mode. Despite these shortcomings of the work performed study and development that followed has led the development of a memory controller on AMBA-AHB bus at a very advanced stage and next to prototyping. VHDL code is utilized to develop the design and it is synthesized in Xilinx Virtex 6 device (XC6VCX75T). The design claims a minor area overhead with improvement in speed 185.134 MHz.
AMBA, AHB Master, AHB Slave, SOC, Xilinx
Короткий адрес: https://sciup.org/15015890
IDR: 15015890 | DOI: 10.5815/ijem.2019.04.03
Список литературы Memory controller and its interface using AMBA 2.0
- Shilpa Rao and Arati S. Phadke, “Implementation of AMBA compliant Memory Controller on a FPGA”, IJETEE, 2013.
- Archana C. Sharma1, Prof.Zoonubiya Ali, “Construct High-Speed SDRAM Memory Controller Using Multiple FIFO's for AHB Memory Slave Interface”, IJETAE, 2013.
- S. Lakshma Reddy, A. Krishna Kumari, “Architecture of an AHB Compliant SDRAM Memory Controller”, International Journal of Innovations in Engineering and Technology, 2013.
- Arun G, Vijaykumar T, “Improving Memory Access time by Building an AMBA AHB compliant Memory Controller”, IJARCET, 2012.
- S. Ramakrishna, K. Venugopal, B. Vijay Bhasker, R. Surya Prakash Rao, “HDL Implementation of AMBA-AHB Compatible Memory Controller”, IJCER, 2012.
- Jayapraveen. D and T. GeethaPriya, “Design of memory controller based on AMBA AHB protocol”, Elixir International Journal, 2012.
- Ch.Vijayalakshmi, Mr B.Raghavaiah, “Implementation of AMBA AHB Compliant Memory Controller with Peripherals”, ICITEC, 2012.
- KareemullahShaik, Mohammad Mohiddin, Md. Zabirullah, “A Reduced Latency Architecture for Obtaining High System Performance”, IJRTE, 2012.
- Hu Yueli; Yang Ben, “Building an AMBA AHB Compliant Memory Controller”, IEEE, 2011.
- VarshaVishwarkama, Abhishekchoubey, ArvindSahu, “Implementation of AMBA AHB protocol for high capacity memory management using VHDL”, IJCSE, 2011.
- Zhao, B., “High speed DDR memory interface design”, IEEE, 2009.
- McGee, S.W.; Klenke, R.H.; Aylor, J.H.; Schwab, A.J., “Design of a processor bus interface ASIC for the stream memory controller”, IEEE, 1994.
- Datta and V. Singhal, \Formal veri_cation of a public-domain ddr2 controller de-sign," VLSI Design, 2008. VLSID 2008. 21st International Conference on, pp. 475{480,Jan. 2008.
- KeesGoossens, Om Prakash Gangwal, Jens R¨over, and A. P. Niranjan. Interconnectand Memory Organization in SOCs for advanced Set-Top Boxesand TV-Evolution, Analysis, and Trends. In JariNurmi, HannuTenhunen, JouniIsoaho, and Axel Jantsch, editors, Interconnect-Centric Design for Advanced SoC and NoC, chapter 15, pages 399–423. Kluwer, April 2004.
- Arm AMBA 2 speciation. [Online]. Available at: http://www.arm.com/products/solutions/AMBA Spec.html
- ShashisekharRamagundam, Sunil R. Das, Scott Morton, Satyendra N. Biswas, VoicuGroza, Mansour H. Assaf, and Emil M. Petriu, “Design and Implementation of High-Performance Master/Slave Memory Controller with Microcontroller Bus Architecture”, IEEE International Conference on Instrumentation and Measurement Technology (I2MTC) Proceedings, pp. 10 – 15, May 2014.
