A Comparative Performance Analysis of Low Power Bypassing Array Multipliers
Автор: Nirlakalla Ravi, S. Venkateswarlu, T. Jayachandra Prasad, Thota Subba Rao
Журнал: International Journal of Information Technology and Computer Science(IJITCS) @ijitcs
Статья в выпуске: 8 Vol. 5, 2013 года.
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Low power design of VLSI circuits has been identified as vital technology in battery powered portable electronic devices and signal processing applications such as Digital Signal Processors (DSP). Multiplier has an important role in the DSPs. Without degrading the performance of the processor, low power parallel multipliers are needed to be design. Bypassing is the widely used technique in the DSPs when the input operand of the multiplier is zero. A Row based Bypassing Multiplier with compressor at the final addition of the ripple carry adder (RCA) is designed to focus on low power and high speed. The proposed bypassing multiplier with compressor shows high performance and energy efficiency than Kuo multiplier with Carry Save Adder (CSA) at the final RCA.
Bypassing, Low Power, Speed, CSA, RCA, Compressor
Короткий адрес: https://sciup.org/15011939
IDR: 15011939
Список литературы A Comparative Performance Analysis of Low Power Bypassing Array Multipliers
- Sunjoo Hong, Taehwan Roh, and Hoi-Jun Yoo, “A 145µW 8×8 Parallel Multiplier based on Optimized Bypassing Architecture,” IEEE International conference, pp: 1175-1178, 2011.
- Ko-Chi Kuo, Chi-WenChou, “Low power and high speed multiplier design with row bypassing and parallel architecture,” Microelectronics Journal 41, pp: 639–650, 2010.
- Ko-Chi Kuo, Chi-WenChou, “Low power Multiplier with bypassing and tree structure,” IEEE Conference Proceedings, pp: 602–605, 2006.
- Chua-Chin and Gang-Neng Sung, “A Low power 2-Dimensional Bypassing Multiplier Using 0.35um CMOS Technology,” IEEE Proceedings of the Emerging VLSI Technologies and Architectures (ISVLSI’06), 2006.
- Gang-Neng Sung and Chua-Chin, “A power aware 2 dimensional bypassing multiplier using cell-based design flow,” IEEE Conference Proceedings, pp: 3338–3341, 2008.
- Jin-Tai Yan and Zhi-Wei Chen, “Low Power Multiplier Design with Row and Column Bypassing,” IEEE Conference Proceedings, pp: 227–230, 2009.
- Gang-Neng Sung, Yu-Cheng Lu and Chua-Chin Wang, “ A power aware signed 2dimensional bypassing multiplier for video/image processing,” IEEE Conference Proceedings, 2010.
- Dimitris Bekiaris, George Economakos and Kiamal Pekmestzi, “A mixed style multiplier architecture for low dynamic and leakage power dissipation,” IEEE Conference Proceedings, pp: 258-261, 2010.
- Anantha P. Chandrakasan and Robert W. Brodersen, “Minimizing Power Consumption in CMOS Circuits,” pp: 1-64, 1995.
- Farzan Fallah and Massoud Pedram, “Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits,” pp: 1-21.
- Victor Adler and Eby G. Friedman, “Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load,” Analog Integrated Circuits and Signal Processing, 14, 29–39, 1997.
- Y. Taur, “CMOS design near the limit of scaling,” IBM J. Res. & Dev. Vol. 46 no. 2/3 March/May 2002.
- Alvin Joseph J. Tang and Joy Alinda Reyes, “Comparative Analysis of Low Power Multiplier Architectures,” IEEE Fifth Asia Modelling Symposium, pp: 270-274, 2011.
- C. S. Wallace, “Suggestions for a Fast Multiplier,” IEE Transactions on Electron. Computers, EC-13, pp. 14-17, 1964.
- L. Dadda, “Some Schemes for Parallel Multipliers,” Alta Freq., 34:349-356, 1965.
- Shubjit Roy Chowdhury, Aritha Banerjee, Aniruddha Roy, Hiranmay Saha, “Design, Simulation and Testing of a High Speed Multiplication Applications,” IEEE Computer Society, pp. 434 - 438, 2008.
- C.-H. Chang, J. Gu, and M. Zhang, “A review of 0.18-µm full adder performances for tree structured arithmetic circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 6, pp. 686–695, 2005.
- Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, and Cheng-Che Ho, “A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design,” IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 54, no. 5, pp. 1050-1059, 2007.
